Interpreting the Latency Numbers

Interpreting the Latency Numbers There are many DRAM timing parameters used by the memory controller in your PC's chipset (or integrated into AMD processors), but you can adjust only a few parameters in the system BIOS. For DDR and DDR2 memory, vendors specify four minimum timing parameters, measured in memory clock cycles:

• CAS Latency (tCL): Column access (READ) until data is available
• RAS to CAS Delay (tRCD): Row access (ACTIVATE) until CAS (READ)
• RAS Precharge Delay (tRP): Precharge until row access (ACTIVATE)
• Precharge Delay (tRAS): Row access (ACTIVATE) until precharge

For instance, a high-performance DDR memory module with 2-2-2-5 timing would have a minimum CAS latency of 2 clocks, a RAS to CAS delay of 2 clocks, a RAS precharge delay of 2 clocks, and a precharge delay of 5 clocks. A high-performance DDR2 module might have 5-5-5-12 timing, illustrating the point that latency (when measured in memory clocks) has actually increased in the latest memory generation DDR2 may have more clock cycles of latency, but the clock rates will scale much higher than with DDR because of slightly relaxed timing constraints and improved signal integrity. More importantly, lower voltages and smaller page sizes have cut back on the power consumed by an active page. Lower-power architecture becomes important as DDR2 speeds scale to 800 MHz, even though the underlying memory cell will still run at a measly 200 MHz. .